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IN74HC393
DUAL 4-STAGE BINARY RIPPLE COUNTER
High-Performance Silicon-Gate CMOS
The IN74HC393 is identical in pinout to the LS/ALS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two independent 4-bit binary ripple counters with parallel outputs from each counter stage. A/256 counter can be obtained by cascading the two binary counters. Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the counters is asynchronous and activehigh. State changes of the Q outputs do not occur simultaneously becaue of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the IN74HC393. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices
* * * *
ORDERING INFORMATION IN74HC393N Plastic IN74HC393D SOIC TA = -55 to 125 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 14 =VCC PIN 7 = GND
FUNCTION TABLE Inputs Outputs Clock Reset X H L H L No Change L L No Change L No Change L Advance to Next State X = don't care
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IN74HC393
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Current, per Pin mA 25 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure VCC =2.0 V 1) VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IN74HC393
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V 85 125 25 C to C C -55C 1.5 1.5 1.5 VIH Minimum High- VOUT=0.1 V or VCC-0.1 V 2.0 3.15 3.15 3.15 Level Input IOUT 20 A 4.5 4.2 4.2 4.2 Voltage 6.0 0.3 0.3 0.3 VIL Maximum Low - VOUT=0.1 V or VCC-0.1 V 2.0 0.9 0.9 0.9 Level Input IOUT 20 A 4.5 1.2 1.2 1.2 Voltage 6.0 1.9 1.9 1.9 VOH Minimum High- VIN=VIH or VIL 2.0 4.4 4.4 4.4 Level Output IOUT 20 A 4.5 5.9 5.9 5.9 Voltage 6.0 VIN=VIH or VIL 3.7 3.84 3.98 IOUT 4.0 mA 4.5 5.2 5.34 5.48 6.0 IOUT 5.2 mA 0.1 0.1 0.1 VOL Maximum Low- VIN=VIH or VIL 2.0 0.1 0.1 0.1 Level Output IOUT 20 A 4.5 0.1 0.1 0.1 Voltage 6.0 VIN=VIH or VIL 0.4 0.33 0.26 IOUT 4.0 mA 4.5 0.4 0.33 0.26 6.0 IOUT 5.2 mA IIN Maximum Input VIN=VCC or GND 6.0 0.1 1.0 1.0 Leakage Current VIN=VCC ICC Maximum or GND 6.0 8.0 80 160 Quiescent Supply IOUT=0A Current (per Package)
Unit
V V V
V
A A
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IN74HC393
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 85C 125 25 C to C -55C 3.6 4.4 5.4 fmax Maximum Clock Frequency (50% Duty 2.0 18 22 27 Cycle) (Figures 1 and 3) 4.5 21 26 32 6.0 180 150 120 tPLH, Maximum Propagation Delay, Clock to 2.0 36 30 24 tPHL Q1 (Figures 1 and 3) 4.5 31 26 20 6.0 285 240 190 tPLH, Maximum Propagation Delay, Clock to 2.0 57 48 38 tPHL Q2 (Figures 1 and 3) 4.5 48 41 32 6.0 360 300 240 tPLH, Maximum Propagation Delay, Clock to 2.0 72 60 48 tPHL Q3 (Figures 1 and 3) 4.5 61 51 41 6.0 435 365 290 tPLH, Maximum Propagation Delay, Clock to 2.0 87 73 58 tPHL Q4 (Figures 1 and 3) 4.5 74 62 49 6.0 250 205 165 tPHL Maximum Propagation Delay, Reset to 2.0 50 41 33 any Q (Figures 2 and 3) 4.5 43 35 28 6.0 110 95 75 tTLH, tTHL Maximum Output Transition Time, Any 2.0 22 19 15 4.5 Output 19 16 13 6.0 (Figures 1 and 3) CIN Maximum Input Capacitance 10 10 10 Power Dissipation Capacitance (Per Typical @25C,VCC=5.0 V Counter) 40 CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 C to85C 125C 55C 75 65 50 trec Minimum Recovery Time, 2.0 15 13 10 Reset Inactive to Clock (Figure 4.5 13 11 9 6.0 2) 120 100 80 tw Minimum Pulse Width, Clock 2.0 24 20 16 (Figure 1) 4.5 20 17 14 6.0 190 155 125 tw Minimum Pulse Width, Set 2.0 38 31 25 (Figure 2) 4.5 32 26 21 6.0 1000 1000 1000 t r, tf Maximum Input Rise and Fall 2.0 500 500 500 Times (Figure 1) 4.5 400 400 400 6.0
Unit
MH z ns ns ns ns ns ns pF
pF
Unit ns ns ns ns
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IN74HC393
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 4.Test Circuit
EXPANDED LOGIC DIAGRAM
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IN74HC393
TIMING DIAGRAM
COUNT SEQUENCE Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q4 L L L L L L L L H H H H H H H H Outputs Q3 Q2 L L L L L H L H H L H L H H H H L L L L L H L H H L H L H H H H Q1 L H L H L H L H L H L H L H L H
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